1. Field of the Invention
The present invention relates generally to selective fault protection for logic functions in an IC design, and more particularly to a new HDL extension at the RTL for designating particular logic functions as fault tolerant and a method of implementing a fault redundant scheme for those logic functions designated as fault tolerant.
2. Background of the Invention
For the design of integrated circuits (IC) technology on a very large scale, designers typically employ computer aided design (CAD) tools. Hardware description languages (HDLs) or other standard languages are typically used to describe ICs and facilitate the design and simulation of complex digital ICs. Common HDLs include the open languages, VHDL and Verilog. VHDL and Verilog are all-purpose HDLs that utilize abstract data types to define a hardware model at the gate level, the register-transfer level (RTL), or the behavioral level.
At the RTL, a description of the IC written in HDL is typically referred to as the RTL description or the RTL code. At the RTL, a description of the system specifying all registers (whether instantiated or inferred), and combinational logic in between them (using logical statements, etc.) is outlined. The RTL description or code specifies the clock-by-clock behavior of the system. The RTL description or code of an IC describes the circuit in terms of a plurality of digital registers, clocking circuits, and logic elements that are combined to implement the desired function of the circuit.
After creation of the RTL code, a designer uses a logic synthesis tool to map the IC design to a target technology, e.g., a field-programmable gate array (FPGA) or application specific integrated circuit (ASIC). Thereafter, each logic function, e.g., combinational logic block (CLB) for FPGAs, is assigned to a location on the chip and signals are routed with wires on the chip to appropriate other logic functions.
In many prior art ICs, even a single logic fault can cause improper operation resulting in data integrity errors or a system crash. Such a scenario can occur with either a soft error, i.e., temporary fault due to radiation, or a permanent fault. Prior art IC design methodology treats each of the logic functions in an IC design the same and fails to provide a way for providing fault protection to particular logic functions. In addition, providing additional fault protection to all of the logic functions in the IC typically increases the amount of area required by the IC and thus the overall size of the IC.